1) Field of the Invention
This invention relates generally to the fabrication of alignment makes in a semiconductor device and, more particularly, to a method involving shallow trench isolation (STI) using a special mask to clear an insulating layer from over an alignment pattern in a semiconductor substrate and to clear the insulating layer from over Active areas in device areas.
2) Description of the Prior Art
As the level of integration in semiconductor devices has increased, device sizes have become smaller. Along with the trend, device isolation structures for electrical isolation between adjacent devices have also become smaller.
For STI structures, trenches are formed into a semiconductor substrate. Thereafter, the trenches are filled with an insulating material, like an oxide film, to a thickness sufficient to bury the trenches. Subsequently, the insulating materials etched back by a chemical mechanical polishing (CMP) method until the surface of an adjacent active region is exposed, thereby planarizing the whole surface of the semiconductor substrate having the trenches formed thereon. Thus, the device isolation structure is completed. The STI method is free of bird's beaks and has an advantage over the LOCOS structures with respect to minimization of isolation spacing. It possesses, however, a distinct drawback that an alignment pattern necessary for subsequent photolithography steps is not obtained, since not enough step is created on the surface of the semiconductor substrate in the STI structure. Conventionally, when a laser is projected from an aligner of a stepper and reflected on an alignment marks formed on the semiconductor substrate, an interference pattern formed due to the irregularities of the alignment mark pattern. The interference pattern is recognized in a detector, the direction and position of the semiconductor substrate are detected, and then the semiconductor substrate and equipment are adjusted in accordance with the detected direction and position of the semiconductor substrate, thereby performing alignment. However, in the STI, a device isolation oxide film is formed by etching back through using the chemical-mechanical polish method or the like, thus providing a planar semiconductor substrate without any step between the device formation area and the device isolation area.
When an opaque film like a tungsten silicide, used as a gate electrode material, is formed on such a planar surface, an interference pattern due to reflection will not be formed. The alignment of the photolithographic equipment, therefore, is practically difficult to perform.
FIG. 8 shows a top plan view of a preferred location of an alignment mark area 14 between prime dies 17 in a kerf 19 on a substrate 10.
A method for forming alignment mark patterns in a shallow trench isolation (STI) structure using a special mask and conventional technology will now be described in detail, referring to the attached drawings.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,700,732(Jost) shows a method of forming alignment marks in substrates using varying etch depths.
U.S. Pat. No. 5,401,691(Caldwell) shows a method of forming Alignment marks in layers using inverse frames.
U.S. Pat. No. 5,578,519(Cho) shows a method of forming an alignment mark using an STI process. U.S. Pat. No. 5,316,966(Van Der Plas et al. ) shows a method of forming alignment marks using STI processes.
U.S. Pat. No. 5,369,050(Kawai) shows another method of forming alignment marks in isolation areas.